The present invention relates in general to an apparatus and method for increasing semiconductor device density, and more particularly, to arranging semiconductor devices within and over substrates to achieve densely packaged semiconductor structures.
Chip On Board techniques are used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and tape automated bonding (TAB). Flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of electrical terminations or bond pads spaced around an active surface of the flip chip for face down mounting of the flip chip to a substrate. Generally, the flip chip has an active surface having Ball Grid Array (BGA) or PIN Grid Array (PGA) electrical connectors. The BGA comprises an array of minute solder balls disposed on the surface of the flip chip that attaches to the substrate (the attachment surface). The PGA comprises an array of small pins that extend substantially perpendicular from the attachment surface of the flip chip. The pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
With the BGA, the solder or other conductive ball arrangement on the flip chip must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board.
Wirebonding attachment generally begins with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, bond wires are attached, one at a time, to each bond pad on the semiconductor chip and extend to a corresponding lead, trace end or bond pad on the printed circuit board. The bond wires are generally attached using industry-standard wirebonding techniques, such as ultrasonic bonding, thermocompression bonding or thermosonic bonding. Ultrasonic bonding comprises the combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld. Thermocompression bonding comprises the combination of pressure and elevated temperature to form a weld. Thermosonic bonding comprises the combination of pressure, elevated temperature, and ultrasonic vibration bursts to form a weld. The semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape, such as a polyamide, are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and the metal tape leads to prevent contamination.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of devices used to fabricate them tends to decrease due to advances in technology even though the functionality of these products increases. For example, on the average, there is approximately a 10 percent decrease in components for every product generation over the previous generation with equivalent functionality.
In integrated circuit packaging, in addition to component reduction, surface mount technology has demonstrated an increase in semiconductor chip density on a single substrate or board despite the reduction of the number of components. This results in more compact designs and form factors, and significant increase in integrated circuit density. However, greater integrated circuit density is primarily limited by the space or xe2x80x9creal estatexe2x80x9d available for mounting dice on a substrate, such as a printed circuit board.
One method of further increasing integrated circuit density is to stack semiconductor dice vertically. U.S. Pat. No. 5,012,323 issued Apr. 30, 1991 to Farnworth teaches combining a pair of dice mounted on opposing sides of a lead frame. An upper, smaller die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. A lower, larger die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative, film layer. The wirebonding pads on both upper die and lower die are interconnected with gold or aluminum bond wires to the ends of their associated lead extensions. The lower die must be slightly larger than the upper die so that the die pads are accessible from above through a bonding window in the lead frame to allow the gold wire connections to be made to the lead extensions. This arrangement has a major disadvantage from a production standpoint as the same size die cannot be used.
U.S. Pat. No. 5,291,061 issued Mar. 1, 1994 to Ball teaches a multiple stacked dice device containing up to four stacked dice supported on a die-attach paddle of a lead frame. The assembly does not exceed the height of current single die packages and the bond pads of each die are wirebonded to lead fingers. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin adhesive layers between the stacked dice. However, Ball requires long bond wires to electrically connect the stacked dice to the lead frame. These long bond wires increase resistance and may result in bond wire sweep during encapsulation. Also, Ball requires the use of spacers between the dice.
U.S. Pat. No. 5,323,060 issued Jun. 21, 1994 to Fogal et al. (Fogal) teaches a multichip module that contains stacked die devices. The terminals or bond pads of die devices are wirebonded to a substrate or to adjacent die devices. However, as discussed with Ball, Fogal requires long bond wires to electrically connect the stacked dice bond pads to the substrate. Fogal also require the use of spacers between the die.
U.S. Pat. Nos. 5,422,435 and 5,495,398 to Takiar et al. (Takiar) teach stacked dice having bond wires extending to each other and to the leads of a carrier member such as a lead frame. Takiar also has the problem of long bond wires, as well as, requiring specific sized or custom designed dice to achieve a proper stacked combination.
U.S. Pat. No. 5,434,745 issued Jul. 18, 1995 to Shokrgozar et al. (Shokrgozar) discloses a stackable packaging module comprising a standard die attached to a substrate with a spacer frame placed on the substrate to surround the die. The substrate/die/spacer combinations are stacked one atop another to form a stacked assembly. The outer edge of the spacer frame has grooves in which a conductive epoxy is disposed. The conductive epoxy forms electric communication between the stacked layers and/or to the final substrate to which the stacked assembly is attached. However, Shokrgozar requires specialized spacer frames and a substantial number of assembly steps, both of which increase the cost of the final assembly.
U.S. Pat. No. 5,128,831 issued Jul. 7, 1992 to Fox, III et al. (Fox) also teaches a standard die attached to a substrate with a spacer frame placed on the substrate to surround the die. The stacked layers and/or the final substrate are in electric communication with conductive epoxy extending through the spacer frames. However, Fox also requires specialized spacer frames, numerous assembly steps, and is limited in its flexibility to utilize a variety of dice.
Another prior art stacking arrangement is shown in FIG. 1. A plurality of printed circuit boards 10 are stacked on top of each other and on top of a motherboard 12. Each of the printed circuit boards 10 include a semiconductor die 14 mounted to a top surface of each respective printed circuit board 10 using methods known in the art. Bond pads on each die are electrically coupled to each respective printed circuit board 10. The printed circuit boards 10 and the motherboard 12 are electrically and physically coupled together using solder balls 16. It should be apparent that the solder balls 16 must be sufficiently thick so that the printed circuit boards 10 do not contact or interfere with adjacent dies 14. The thick solder balls 16 increase the overall size of the structure and the length of the signal paths.
Accordingly, there is an ongoing need for semiconductor structures having increased circuit density. There is a further need for semiconductor structures in which printed circuit boards are stacked to increase circuit density. There is a still further ongoing need for semiconductor structures having shorter signal paths. Preferably, such semiconductor structures are relatively inexpensive, easy to manufacture, and use standard die configurations and components.
The present invention meets these needs by providing a semiconductor structure in which flip chips or other semiconductor devices are mounted on printed circuit boards. The printed circuit boards are stacked to increase the circuit density of the semiconductor structure. The printed circuit boards include cavities or openings to accommodate the flip chips or semiconductor devices and thus reduce the overall size of the semiconductor structure. The flip chips or semiconductor devices from adjacent printed circuit boards may extend into the cavities or openings or simply occupy the cavities or openings from the same printed circuit board.
According to a first aspect of the present invention, a semiconductor structure comprises a base substrate, a first substrate and at least one semiconductor. The base substrate comprises a first surface having a first plurality of base substrate bond pads formed thereon. The first substrate comprises a first surface, a second surface and at least one cavity formed therein. One of the first and second surfaces includes a first plurality of first substrate bond pads. At least one of the first plurality of first substrate bond pads is electrically coupled to at least one of the first plurality of base substrate bond pads. The semiconductor device includes a plurality of semiconductor device bond pads. The semiconductor device is positioned generally within the cavity of the first substrate between the base substrate and the first substrate with at least one of the plurality of semiconductor device bond pads electrically coupled to at least one of the first plurality of base substrate bond pads.
The other of the first and second surfaces of the first substrate may comprise a second plurality of first substrate bond pads while the semiconductor structure may further comprise a second semiconductor device having a plurality of second semiconductor device bond pads. At least one of the plurality of second semiconductor device bond pads is electrically coupled to at least one of the second plurality of first substrate bond pads. A center of the at least one semiconductor device and a center of the second semiconductor device may be substantially aligned about a line substantially perpendicular to the base substrate and the first substrate.
The semiconductor structure may further comprise a plurality of semiconductor devices, each comprising a plurality of bond pads formed thereon. The first substrate may comprise a plurality of cavities with each of the plurality of semiconductor devices being positioned within respective ones of the plurality of cavities and at least one of the plurality of bond pads of each of the plurality of semiconductor devices electrically coupled to respective ones of the plurality of bond pads of the base substrate. The semiconductor device may comprise a semiconductor die formed within a semiconductor package. The semiconductor package may comprise a package selected from the group consisting of a chip-scale package, a ball grid array, a chip-on-board, a direct chip attach, and a flip-chip.
Preferably, the semiconductor device is electrically and physically coupled to the base substrate via solder balls coupling at least one of the plurality of semiconductor device bond pads to at least one of the first plurality of base substrate bond pads. The first substrate is preferably electrically and physically coupled to the base substrate via solder balls coupling at least one of the first plurality of first substrate bond pads to at least one of the first plurality of base substrate bond pads. The base substrate may further comprise a second surface having a second plurality of base substrate bond pads formed thereon. Preferably, at least one of the second plurality of base substrate bond pads is electrically coupled to external circuitry. The base substrate may further comprise a plurality of base substrate trace leads electrically coupling at least a portion of the first plurality of base substrate bond pads to at least a portion of the second plurality of base substrate bond pads.
According to another aspect of the present invention, a semiconductor structure comprises a base substrate, a first substrate, a second substrate, a first semiconductor device and a second semiconductor device. The base substrate includes a first surface having a first plurality of base substrate bond pads formed thereon and a second surface having a second plurality of base substrate bond pads formed thereon. The base substrate further comprises a plurality of base substrate trace leads electrically coupling at least a portion of the first plurality of base substrate bond pads to at least a portion of the second plurality of base substrate bond pads. The first substrate includes a first surface, a second surface, and at least one cavity formed therein. The first surface of the first substrate comprises a first plurality of first substrate bond pads formed thereon and the second surface of the first substrate comprises a second plurality of first substrate bond pads formed thereon. The first substrate is electrically and physically coupled to the base substrate via solder balls coupling at least one of the first plurality of first substrate bond pads to at least one of the first plurality of base substrate bond pads. The second substrate includes a first surface, a second surface, and at least one cavity formed therein. The first surface of the second substrate includes a first plurality of second substrate bond pads formed thereon and the second surface of the second substrate comprises a second plurality of second substrate bond pads formed thereon. The second substrate is electrically and physically coupled to the first substrate via solder balls coupling at least one of the second plurality of first substrate bond pads to at least one of the first plurality of second substrate bond pads. The first semiconductor device includes a plurality of first semiconductor device bond pads formed thereon. The first semiconductor device is positioned generally within the cavity of the first substrate and is physically and electrically coupled to the base substrate via solder balls coupling at least one of the plurality of first semiconductor device bond pads to at least one of the first plurality of base substrate bond pads. The second semiconductor device includes a plurality of second semiconductor device bond pads formed thereon. The second semiconductor device is positioned generally within the cavity of the second substrate and is physically and electrically coupled to the first substrate via solder balls coupling at least one of the plurality of second semiconductor device bond pads to at least one of the second plurality of first substrate bond pads.
According to yet another aspect of the present invention, the semiconductor structure comprises a base substrate, a first substrate and at least one semiconductor device. The base substrate comprises a first surface having a first plurality of base bond pads formed thereon. The first substrate includes a first surface, a second surface and at least one opening formed therein. One of the first and second surfaces includes a first plurality of first substrate bond pads with at least one of the first plurality of first substrate bond pads being electrically coupled to at least one of the first plurality of substrate base bond pads. The semiconductor device includes a plurality of semiconductor device bond pads. The semiconductor device is positioned generally within the opening of the first substrate between the base substrate and the first substrate with at least one of the plurality of semiconductor device bond pads electrically coupled to at least one of the first plurality of base substrate bond pads. Preferably, the semiconductor device is electrically and physically coupled to the base substrate via solder balls coupling at least one of the plurality of semiconductor device bond pads to at least one of the first plurality of base substrate bond pads.
According to a further aspect of the present invention, a semiconductor structure comprises a first substrate, an interconnect device and at least one semiconductor device. The first substrate has at least one opening and a surface including a plurality of first substrate bond pads formed thereon. The interconnect device is positioned over the opening of the first substrate and is coupled thereto. The semiconductor device includes a plurality of semiconductor device bond pads. The semiconductor device is positioned generally over the opening of the first substrate and is coupled to the interconnect device.
The interconnect device may comprise a plurality of contacts with at least one of the plurality of contacts being electrically coupled to at least one the plurality of semiconductor device bond pads. At least one of the plurality of contacts is preferably electrically coupled to at least one the plurality of first substrate bond pads.
According to a still further aspect of the present invention, a semiconductor structure comprises a base substrate, a first substrate, a first semiconductor device and a second semiconductor device. The base substrate includes a first surface having a first plurality of base bond pads formed thereon. The first substrate includes a first surface having a first plurality of first substrate bond pads, a second surface having a second plurality of first substrate bond pads, and at least one opening formed therein. At least one of the first plurality of first substrate bond pads is electrically coupled to at least one of the first plurality of base substrate bond pads. The interconnect device is positioned over the opening of the first substrate and is coupled to the first substrate. The first semiconductor device includes a plurality of first semiconductor device bond pads. The first semiconductor device is positioned generally within the opening of the first substrate between the base substrate and the first substrate with at least one of the plurality of first semiconductor device bond pads electrically coupled to at least one of the first plurality of base substrate bond pads. The second semiconductor device includes a plurality of second semiconductor device bond pads. The second semiconductor device is positioned generally over the opening of the first substrate and is coupled to the interconnect device.
Preferably, the interconnect structure is electrically and physically coupled to the second surface of the first substrate. At least one of the second semiconductor device bond pads is electrically coupled to the first substrate through the interconnect device. The first substrate may further comprise a plurality of first substrate trace leads electrically coupling at least a portion of the first plurality of first substrate bond pads to respective ones of a first plurality of contacts on the interconnect device. At least one of the second semiconductor device bond pads may be electrically coupled to the first substrate via a bond wire. The interconnect structure may comprise a flex circuit or TAB tape. The semiconductor structure may further comprise a plurality of the first substrates, a plurality of the first semiconductor devices and a plurality of interconnect devices.
According to a yet still further aspect of the present invention, a semiconductor structure comprises a base substrate, a first substrate, a second substrate, a first interconnect device, a second interconnect device, a first semiconductor device, a second semiconductor device and a third semiconductor device. The base substrate includes a first surface having a first plurality of base substrate bond pads formed thereon and a second surface having a second plurality of base substrate bond pads formed thereon. The base substrate further comprises a plurality of base substrate trace leads electrically coupling at least a portion of the first plurality of base substrate bond pads to at least a portion of the second plurality of base substrate bond pads. The first substrate includes a first surface, a second surface and at least one opening formed therein. The first surface of the first substrate comprises a first plurality of first substrate bond pads formed thereon and the second surface of the first substrate comprises a second plurality of first substrate bond pads formed thereon. The first substrate is electrically and physically coupled to the base substrate via solder balls coupling at least one of the first plurality of first substrate bond pads to at least one of the first plurality of base substrate bond pads. The first substrate further comprises a plurality of first substrate trace leads electrically coupling at least a portion of the first plurality of first substrate bond pads to at least a portion of the second plurality of first substrate bond pads. The second substrate includes a first surface, a second surface and at least one opening formed therein. The first surface of the second substrate comprises a first plurality of second substrate bond pads formed thereon and the second surface of the second substrate comprises a second plurality of second substrate bond pads formed thereon. The second substrate is electrically and physically coupled to the first substrate via solder balls coupling at least one of the first plurality of second substrate bond pads to at least one of the second plurality of first substrate bond pads. The second substrate further comprises a plurality of second substrate trace leads electrically coupling at least a portion of the first plurality of second substrate bond pads to at least a portion of the second plurality of second substrate bond pads. The first interconnect device is positioned over the opening of the first substrate and is physically and electrically coupled to the first substrate. The first interconnect structure comprises a plurality of first interconnect device contacts. The second interconnect device is positioned over the at least one opening of the second substrate and physically and electrically coupled to the second substrate. The second interconnect structure also comprises a plurality of second interconnect device contacts. The first semiconductor device includes a plurality of first semiconductor device bond pads. The first semiconductor device is positioned within the opening of the first substrate between the base substrate and the first substrate and is physically and electrically coupled to the base substrate via solder balls coupling at least one of the plurality of first semiconductor device bond pads to at least one of the first plurality of base substrate bond pads. The second semiconductor device includes a plurality of second semiconductor device bond pads. The second semiconductor device is positioned within the opening of the second substrate between the first substrate and the second substrate and is physically and electrically coupled to the first interconnect device via solder balls coupling at least one of the plurality of second semiconductor device bond pads to at least one of the plurality of first interconnect device contacts. The third semiconductor device includes a plurality of third semiconductor device bond pads. The third semiconductor device is physically and electrically coupled to the second interconnect device via solder balls coupling at least one of the plurality of third semiconductor device bond pads to at least one of the plurality of second interconnect device contacts.
According to another aspect of the present invention, a semiconductor structure comprises a first substrate, an interconnect device and at least one semiconductor device. The first substrate includes at least one opening and a surface including a plurality of first substrate bond pads. The interconnect device is positioned over the opening of the first substrate and is coupled to the first substrate. The semiconductor device includes a plurality of semiconductor device bond pads. The semiconductor device is positioned generally within the opening of the first substrate and is coupled to the interconnect device. The interconnect device may be electrically non-conductive. The interconnect device may not be electrically coupled to the first substrate such that at least one of the plurality of semiconductor bond pads is electrically coupled to at least one of the plurality of first substrate bond pads via a bond wire. The interconnect device may comprise a flex circuit.
According to yet another aspect of the present invention, a semiconductor structure comprises a base substrate, a first substrate, a second substrate, a first interconnect device, a second interconnect device, a first semiconductor device and a second semiconductor device. The base substrate includes a first surface having a first plurality of base substrate bond pads formed thereon. The first substrate includes a first surface having a first plurality of first substrate bond pads, a second surface having a second plurality of first substrate bond pads, and at least one opening. At least one of the first plurality of first substrate bond pads is electrically coupled to at least one of the first plurality of base substrate bond pads. The second substrate includes a first surface having a first plurality of second substrate bond pads, a second surface having a second plurality of second substrate bond pads, and at least one opening. At least one of the first plurality of second substrate bond pads is electrically coupled to at least one of the second plurality of first substrate bond pads. The first interconnect device is positioned over the opening of the first substrate and is coupled to the first substrate. The second interconnect device is positioned over the opening of the second substrate and is coupled to the second substrate. The first semiconductor device includes a plurality of first semiconductor device bond pads. The first semiconductor device is positioned generally within the opening of the first substrate and is coupled to the first interconnect device. The second semiconductor device includes a plurality of second semiconductor device bond pads. The second semiconductor device is positioned generally within the opening of the second substrate and is coupled to the second interconnect device.
The first interconnect device may be physically but not electrically coupled to the first surface of the first substrate. The first interconnect device may be physically but not electrically coupled to the first semiconductor device. At least one of the plurality of first semiconductor bond pads is electrically coupled to at least one of the second plurality of first substrate bond pads via a bond wire. The plurality of first semiconductor device bond pads may be positioned on a frontside of the first semiconductor device. A backside of the first semiconductor device may be electrically coupled to the first interconnect device and at least one of the plurality of first semiconductor bond pads may be electrically coupled to at least one of the second plurality of first substrate bond pads via a bond wire.
According to yet another aspect of the present invention, a method of manufacturing a semiconductor structure comprises providing a base substrate having a first surface. A first plurality of base substrate bond pads are formed on the first surface of the base substrate. A first substrate is provided having a first surface, a second surface, and at least one cavity formed within the first surface of the first substrate. A first plurality of first substrate bond pads are formed on the first surface of the first substrate. At least one semiconductor device is provided having a plurality of semiconductor device bond pads. At least one of the plurality of semiconductor device bond pads is coupled to at least one of the first plurality of base substrate bond pads. The first substrate is positioned over the first surface of the base substrate such that the semiconductor device is generally within the cavity of the first surface. At least one of the first plurality of first substrate bond pads is coupled to at least one of the first plurality of base substrate bond pads.
According to a further aspect of the present invention, a method of manufacturing a semiconductor structure comprises providing a first substrate having at least one opening. A plurality of first substrate bond pads are formed on a surface of the first substrate. An interconnect device is provided. The interconnect device is coupled to the first substrate generally over the opening of the substrate. At least one semiconductor device is provided having a plurality of semiconductor device bond pads. The semiconductor device is coupled to the interconnect device generally over the opening of the first substrate.
According to another aspect of the present invention, a method of manufacturing a semiconductor structure comprises providing a first substrate having at least one opening. A plurality of first substrate bond pads are formed on a surface of the first substrate. An interconnect device is provided. The interconnect device is coupled to the first substrate generally over the opening of the first substrate. At least one semiconductor device is provided having a plurality of semiconductor device bond pads. The semiconductor device is coupled to the interconnect device generally within the opening of the first substrate.
Accordingly, it is an object of the present invention to provide a semiconductor structure having increased circuit density. It is another object of the present invention to provide a semiconductor structure having shorter signal paths. Preferably, such semiconductor structures are relatively inexpensive, easy to manufacture and use standard dies and components. Other features and advantages of the invention will be apparent from the following description, the accompanying drawings and the appended claims.